As semiconductor technologies continue to increase the speed at which ICs operate, at-speed (i.e. at full operational speed) testing at both the IC and circuit board level becomes more difficult. Traditionally, boards are tested at-speed using functional test equipment. The cost of purchasing high speed functionality testers capable of keeping up with state of the art board designs, is rapidly escalating. A new approach is needed to allow more of the IC and board testing to be performed inside the ICs themselves, rather than using external test hooks and expensive test equipment.
The invention provides a novel approach in performing atspeed concurrent testing at the IC or circuit board level. The ability to apply tests during normal operation, allows failures that may occur due to the interaction of ICs on a circuit board assembly, to be detected. These types of failures are very difficult to detect using off-line test techniques since the circuit behavior is modified. When performing off-line testing, a circuit is reconfigured from a functional mode to a test mode. In the test mode the circuit may exhibit a different behavioral characteristic. Thus timing sensitive failures, as well as other subtle failures, are shielded from detection.
To implement at-speed concurrent testing, a means of system level qualification is necessary. The present invention provides a Global Event Qualification Structure (GEQS) that can be implemented into IC designs to provide the timing and control features requird to activate the test logic in one or more ICs on a circuit board assembly. The basis of this structure is achieved by bordering an IC's inputs and outputs with unique comparator cells, referred to as Event Qualifier CELLS (EQCELLs).
The EQCELLs compare the data entering and/or leaving an IC to a set of predetermined compare vectors that are loaded into each EQCELL. Each EQCELL may contain a plurality of scan cells that are loaded during a scan operation. In turn, an EQCELL generates a control signal when a comparison is true.
It is an object of the present invention to provide a mechanism for determining when a selected input and/or output has occurred without interfering with normal operations.
In most instances, it is desirable to know when a given set of inputs and/or outputs has occurred on a particular IC. Therefore an IC may have a plurality of EQCELLs, wherein each input and/or output may have an EQCELL associated with it. The EQCELLs can then be preset to compare for a combination of ones and zeros. All EQCELLs' outputs are then combined to yield a composite output designated the local product term (or EQOUT).
It is an object of the present invention to provide a means for loading a data pattern into a selected set of EQCELLs.
It is also an object of the present invention to generate a local product term indicative of a match between incoming and/or outgoing data of the IC and a preselected pattern.
To test on a larger scale than just one IC, it is desirable to be able to know when a set of input and/or outputs has occurred on more than one IC. Therefore, external logic can be used to combine multiple local product terms into a global product term.
It is an object of the present invention to test for a given pattern of inputs and/outputs on multiple logic circuits without interference of normal operations.
It is also an object of the invention to generate a global product term indicative of multiple product terms showing a match of input and/or output with a preselected pattern.
While knowing when a single even has occurred is all that is require for some forms of testing, there are other types where it is also necessary to know when a second event (i.e. a stop test pattern) has occurred. Therefore the present invention may allow two bits (a START and a STOP) to be input into each EQCELL. The advantage in allowing two comparisons to be stored is speed. Since the invention provides for testing to be performed concurrently with normal operation of the circuit, having the two patterns pre-loaded eliminates the risk of having the second event occur before re-loading the EQCELLs.
It is an object of the invention to allow testing to be performed concurrently with normal operation of a logic circuit.
It is also an object of the invention to provide for a start pattern and a stop pattern to be pre-loaded into the EQCELLs.
For some tests, the status of certain inputs and/or outputs is irrelevant or may lead to a delay in detecting the desired I/O condition. The present invention thus can allow an additional bit (referred to as a MASK) to be set in the EQCELL. This in turn will force the EQCELL to always generate a true comparison condition.
It is an object of the invention to allow preselected I/O conditions to be ignored while continuing to check for other conditions.
The invention also provides for local controllers contained within an IC or at a more global level. When a start test condition is met, then the local controller can activate test logic. When a stop pattern is received, then the local controller can terminate the test, signal other circuitry to perform additional functions, and/or cause a reset among other things. The advantages to having local controllers include; minimizing bus wiring, reducing timing delays by having fewer gates and shorter path lengths, and allowing concurrent testing among various logic areas in the system.
It is an object of the present invention to include provisions for local test controllers.
It is also an object of the invention to allow local test functions to be managed by local test controllers.
These and other objects are achieved by:
A test system comprising:
a logic circuit having input and output adapted for signal data;
selected ones of said logic circuit's input and output having a test cell coupled thereto;
each said test cell having at least one storage for storing a condition;
each said test cell also having a comparator for comparing said signal data with said stored condition; and
said comparator generating a control signal indicating a true comparison between said signal data and said stored condition, wherein said control signal is used to effectuate testing of said logic circuit.